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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>E:\FPGA\Tang20K\ethernet\ethernet\src\eth_udp_mii\crc32_d4.v<br>
E:\FPGA\Tang20K\ethernet\ethernet\src\eth_udp_mii\eth_udp_mii.v<br>
E:\FPGA\Tang20K\ethernet\ethernet\src\eth_udp_mii\ip_receive.v<br>
E:\FPGA\Tang20K\ethernet\ethernet\src\eth_udp_mii\ip_send.v<br>
E:\FPGA\Tang20K\ethernet\ethernet\src\eth_udp_rmii\mii_to_rmii.v<br>
E:\FPGA\Tang20K\ethernet\ethernet\src\eth_udp_rmii\rmii_to_mii.v<br>
E:\FPGA\Tang20K\ethernet\ethernet\src\ethernet_top.v<br>
E:\FPGA\Tang20K\ethernet\ethernet\src\fifo_2048x32\fifo_2048x32.v<br>
E:\FPGA\Tang20K\ethernet\ethernet\src\mdio_rtl8201\mdio.v<br>
E:\FPGA\Tang20K\ethernet\ethernet\src\mdio_rtl8201\rtl8201_initialize.v<br>
E:\FPGA\Tang20K\ethernet\ethernet\src\pll_1m\pll_1m.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-4 Education</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Dec 11 23:07:13 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>ethernet_top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.335s, Peak memory usage = 84.031MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 84.031MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 84.031MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 84.031MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 84.031MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 84.031MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 84.031MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 84.031MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 84.031MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 84.031MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 84.031MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 84.031MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.11s, Peak memory usage = 84.031MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 84.031MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 84.031MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>18</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>18</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>11</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIOBUF</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>542</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>67</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>16</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>17</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>28</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>107</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>305</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDLCE</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>752</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>109</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>221</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>422</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>131</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>131</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>26</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>26</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>CLOCK </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsprPLL</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>909(778 LUT, 131 ALU) / 20736</td>
<td>5%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>542 / 16173</td>
<td>4%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>1 / 16173</td>
<td><1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>541 / 16173</td>
<td>4%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>4 / 46</td>
<td>9%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>sys_clk</td>
<td>Base</td>
<td>37.037</td>
<td>27.0</td>
<td>0.000</td>
<td>18.519</td>
<td> </td>
<td> </td>
<td>sys_clk_ibuf/I </td>
</tr>
<tr>
<td>eth_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>eth_clk_ibuf/I </td>
</tr>
<tr>
<td>fifo_2048x32_inst/fifo_inst/n4_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/O </td>
</tr>
<tr>
<td>fifo_2048x32_inst/fifo_inst/n9_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>fifo_2048x32_inst/fifo_inst/n9_s2/O </td>
</tr>
<tr>
<td>clk_25m_3</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>clk_25m_s0/Q </td>
</tr>
<tr>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F </td>
</tr>
<tr>
<td>n50_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>n50_s2/O </td>
</tr>
<tr>
<td>pll_1m_0/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>1000.000</td>
<td>1.0</td>
<td>0.000</td>
<td>500.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>pll_1m_0/rpll_inst/CLKOUTD </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/n4_6</td>
<td>100.0(MHz)</td>
<td>771.6(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>fifo_2048x32_inst/fifo_inst/n9_6</td>
<td>100.0(MHz)</td>
<td>1984.1(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>clk_25m_3</td>
<td>100.0(MHz)</td>
<td>143.6(MHz)</td>
<td>10</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>n50_6</td>
<td>100.0(MHz)</td>
<td>771.6(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>5</td>
<td>pll_1m_0/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>1.0(MHz)</td>
<td>295.2(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.572</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>370.591</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.163</td>
</tr>
<tr>
<td class="label">From</td>
<td>eth_udp_mii_inst/ip_receive_inst/receive_right_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rled_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_25m_3[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_25m_3</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>447</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>370.180</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>eth_udp_mii_inst/ip_receive_inst/receive_right_s0/CLK</td>
</tr>
<tr>
<td>370.411</td>
<td>0.231</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>eth_udp_mii_inst/ip_receive_inst/receive_right_s0/Q</td>
</tr>
<tr>
<td>370.591</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rled_4_s0/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>sys_clk</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>371.233</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rled_4_s0/CLK</td>
</tr>
<tr>
<td>371.198</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>rled_4_s0</td>
</tr>
<tr>
<td>371.163</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>rled_4_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.683</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 43.796%; tC2Q: 0.231, 56.204%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.168</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.942</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.110</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_25m_3[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>5.237</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>5.469</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>5.706</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/n30_s1/I2</td>
</tr>
<tr>
<td>6.159</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>fifo_2048x32_inst/fifo_inst/n30_s1/F</td>
</tr>
<tr>
<td>6.396</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_2_s3/I0</td>
</tr>
<tr>
<td>6.913</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_2_s3/F</td>
</tr>
<tr>
<td>7.150</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_2_s0/I1</td>
</tr>
<tr>
<td>7.705</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_2_s0/F</td>
</tr>
<tr>
<td>7.942</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_2_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_25m_3</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>447</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>10.180</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_2_s0/CLK</td>
</tr>
<tr>
<td>10.145</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>fifo_2048x32_inst/fifo_inst/wptr_2_s0</td>
</tr>
<tr>
<td>10.110</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_2_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.057</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.237, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.525, 56.377%; route: 0.948, 35.046%; tC2Q: 0.232, 8.577%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.237, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.206</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.904</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.110</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_25m_3[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>5.237</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>5.469</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>5.706</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>6.159</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>6.396</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_7_s1/I0</td>
</tr>
<tr>
<td>6.913</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_7_s1/F</td>
</tr>
<tr>
<td>7.150</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_7_s3/I0</td>
</tr>
<tr>
<td>7.667</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_7_s3/F</td>
</tr>
<tr>
<td>7.904</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_7_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_25m_3</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>447</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>10.180</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_7_s0/CLK</td>
</tr>
<tr>
<td>10.145</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_7_s0</td>
</tr>
<tr>
<td>10.110</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_7_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.057</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.237, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.487, 55.755%; route: 0.948, 35.546%; tC2Q: 0.232, 8.699%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.237, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.206</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.904</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.110</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_25m_3[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>5.237</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>5.469</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>5.706</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>6.159</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>6.396</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/I0</td>
</tr>
<tr>
<td>6.913</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/F</td>
</tr>
<tr>
<td>7.150</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_8_s3/I0</td>
</tr>
<tr>
<td>7.667</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_8_s3/F</td>
</tr>
<tr>
<td>7.904</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_8_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_25m_3</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>447</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>10.180</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_8_s0/CLK</td>
</tr>
<tr>
<td>10.145</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_8_s0</td>
</tr>
<tr>
<td>10.110</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_8_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.057</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.237, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.487, 55.755%; route: 0.948, 35.546%; tC2Q: 0.232, 8.699%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.237, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.206</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.904</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.110</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_25m_3[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>5.237</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>5.469</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>5.706</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>6.159</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>6.396</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/I0</td>
</tr>
<tr>
<td>6.913</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/F</td>
</tr>
<tr>
<td>7.150</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_9_s3/I0</td>
</tr>
<tr>
<td>7.667</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_9_s3/F</td>
</tr>
<tr>
<td>7.904</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_9_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_25m_3</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>447</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>10.180</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_9_s0/CLK</td>
</tr>
<tr>
<td>10.145</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_9_s0</td>
</tr>
<tr>
<td>10.110</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_9_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.057</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.237, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.487, 55.755%; route: 0.948, 35.546%; tC2Q: 0.232, 8.699%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.237, 100.000%</td></tr>
</table>
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